Analog-to-digital and digital-to-analog converters designed for digital audio applications frequently support a three-wire, serial interface for stereo (two channel) digital audio data. A typical timing diagram for a serial interface is shown in FIG. 1. This interface consists of a serial data stream (SDATA), a serial clock (SCLK), and a frame clock or left/right clock (LRCK). In an analog-to-digital converter, the serial data (SDATA) is generated by the part, and the serial data clock (SCLK) may be generated by the part or by a separate part. In a digital-to-analog converter, the serial data (SDATA) and serial clock (SCLK) are provided by the user. In both cases, the user is typically required to provide the left/right clock (LRCK), and in many converters the user must also provide a master clock (MCLK) at an integer multiple of the LRCK frequency. The serial data stream contains data for both left and right channels in an interleaved format. When LRCK is high, a sample of the left channel signal is presented, and when LRCK is low, a sample of the right channel signal is presented. The frequency of the LRCK clock is therefore equal to the sampling rate (Fs) of the left and right channel PCM (Pulse Code Modulation) data. The serial clock frequency is typically an integer multiple of the left/right clock, such as 32x or 64x Fs. The master clock is typically at a rate of 256x, 384x, or 512x Fs.
While this three-wire serial interface is widely used, there is a multiplicity of data formats which are in common use. The potential variations in serial data format can be summarized as follows:
1. the sense of the LRCK (left channel during LRCK high or left channel during LRCK low),
2. whether data is presented MSB (Most Significant Bit) first or LSB (Least Significant Bit) first,
3. whether the data is left justified or right justified relative to the LRCK transitions,
4. the number of data bits per channel, typically 16, 18, or 20,
5. the number of SCLK cycles which are expected during one LRCK period,
6. the edge of the SCLKwhich defines when the serial data is latched,
7. whether the first data bit is delayed one SCLK period after the leading LRCK edge, or not.
Many commercial parts are able to operate with more than one of these competing serial data formats in order to provide a higher degree of system compatibility. When a multiplicity of serial formats are supported, the user is required to select the desired format either by programming the part by hard wiring external pins, or by using an available programming port. In either case, these programming means require additional pins on the integrated circuit. In applications where physical space is important, such as portable compact disk (CD) players or in-dash automotive systems, a minimum pin-count is desired to minimize the printed circuit board (PCB) space required by the integrated circuit.
It can therefore be appreciated that a method which allows flexibility of an integrated circuit while keeping the pin-count to a minimum is highly desirable.